1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a gate electrode for a MOSFET, and more particularly to a method of forming a gate electrode with a titanium polycide structure.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line width of a gate electrode and other patterns becomes fine. Recently, the line width is reduced below 0.15 .mu.m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysiliocn layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer, is applied to a semiconductor device of IG DRAM or more.
Here, the titanium silicide layer is formed by two methods as follows.
A first method deposits a titanium (Ti) layer on a polysilicon layer and performs annealing, to react the Ti with Si of the polysilicon layer, thereby forming a titanium silicide (TiSi.sub.2) layer. A second method deposits a TiSi.sub.x layer of an amorphous phase on a polysilicon layer by physical vapor deposition (PVD) using a TiSi.sub.x sputtering target and performs annealing, thereby forming a TiSi.sub.2 layer of a crystalline phase.
FIG. 1A to FIG. 1E are cross sectional views describing a method of forming a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer according to the prior art using the second method.
Referring to FIG. 1A, a gate oxide layer 11 is grown on a semiconductor substrate 10 and a doped polysilicon layer 12 is deposited thereon. Referring to FIG. 1B, a TiSi.sub.x layer 13 of an amorphous phase is deposited on the polysilicon layer 12 by PVD using a TiSi.sub.x target.
Referring to FIG. 1C, rapid thermal process (RTP) is performed at a selected temperature for several seconds to transform the TiSi.sub.x layer 13 of the amorphous phase into a TiSi.sub.2 layer 13a of a crystalline phase. Next, for performing subsequent process such as self-aligned contact (SAC), a mask nitride layer (or oxide layer) is deposited on the TiSi.sub.2 layer 13a.
Referring to FIG. 1D, the mask nitride layer 14, the TiSi.sub.2 layer 13a and the polysilicon layer 12 are etched to form a gate electrode.
Referring to FIG. 1E, for removing damage and polysilicon residues due to the etching process and recovering the reliability of the gate oxide layer 11 by forming a bird's beak, gate re-oxidation process is performed by well known method, so that an oxide layer 15 is formed on the side wall of the gate electrode.
However, when performing the gate re-oxidation process, the side wall portion of the TiSi.sub.2 layer 13a is excessively oxidized, as shown in FIG. 1E, thereby increasing the resistivity of the gate electrode. Here, the oxidation of the TiSi.sub.2 layer 13a is related to the mole ratio x of Si:Ti in the TiSi.sub.x sputtering target. More specifically, while in case the mole ratio x is below 2.1, the TiSi.sub.2 layer is excessively oxidized, in case the mole ratio x is over 2.4, the TiSi.sub.2 layer is moderately oxidized without any deformation. Namely, when silicon content of the TiSi.sub.x sputtering target is stoichiometrically excessive, the oxidation rate of the TiSi.sub.2 layer 13a is equalized to that of the polysilicon layer 12, so that the gate re-oxidation process can be performed.
However, the more the silicon content is high, the more particles increase, so that it is limited to use the TiSi.sub.2 target having silicon content of 2.4 or more.